A DC/DC converter is used for electronic equipment, OA (Office Automation) equipment, and the like. In a DC/DC converter including a high side MOS transistor and a low side MOS transistor, each of which is an N-channel metal oxide semiconductor field effect transistor (NMOSFET), in order to operate the high side MOS transistor appropriately, it is necessary to set a gate-source voltage of the high side MOS transistor to be higher than a drain-source voltage of the high side MOS transistor. To this end, a bootstrap circuit is used in the high side MOS transistor.
FIG. 7 is a schematic circuit diagram of a synchronous rectification step-down DC/DC converter including a conventional bootstrap circuit. Hereinafter, a conventional synchronous rectification step-down/DC converter is described below with reference to FIG. 7.
In FIG. 7, the DC/DC converter includes a control circuit DRV, a first gate driver DR1, a second gate driver DR2, a switching transistor Q1, a synchronous rectification transistor Q2, a series regulator SR, a bootstrap circuit BS, an inductor L, and a capacitor C. A smoothing circuit includes the inductor L and the capacitor C.
The control circuit DRV switches on/off states of the switching transistor Q1 and the synchronous rectification transistor Q2 complementarily by means of a PWM (Pulse Width Modulation) or PFM (Pulse Frequency Modulation) control.
The first gate driver DR1 and the second gate driver DR2 generate a drive signal S1 and a drive signal S2, respectively, in response to control signals from the control circuit DRV, and switch the on/off states of the switching transistor Q1 and the synchronous rectification transistor Q2 complementarily.
NMOS transistors may be used for the switching transistor Q1 and the synchronous rectification transistor Q2. In addition, a parasitic diode D1, which is typically called a body diode, exists between a source and a drain of the switching transistor Q1. Similarly, a parasitic diode D2, which is typically called a body diode, exists between a source and a drain of the synchronous rectification transistor Q2.
The bootstrap circuit BS includes a diode Db and a capacitor Cb. The bootstrap circuit BS is used to generate a voltage to be applied to a power terminal (high voltage potential terminal) of the first gate driver DR1. The voltage is supplied from a node between the diode Db and the capacitor Cb to the power terminal of the first gate driver DR1. Thus, it is possible to increase a voltage to be applied to a gate of the switching transistor Q1. As a result, it is possible to reliably turn on the switching transistor Q1. In addition, a transistor may be used instead of the diode Db.
The series regulator SR includes a third transistor Q3 and an error amplifier ERR. The series regulator SR is a step-down regulator and is used to lower an input voltage to a predetermined output voltage. A P-channel metal oxide semiconductor field effect transistor (PMOSFET) is used for the third transistor Q3.
Next, the circuit configuration and the circuit connection of the DC/DC converter including the bootstrap circuit of FIG. 7 are described below.
Although not shown, the control circuit DRV includes, for example, an error amplifier, a PWM comparator, a phase compensation circuit, various protection circuits, a dead time generation circuit, etc. A first output terminal Do1 of the control circuit DRV is connected to an input terminal of the first gate driver DR1. A second output terminal Do2 of the control circuit DRV is connected to an input terminal of the second gate driver DR2. An output terminal of the first gate driver DR1 is connected to the gate G of the switching transistor Q1. An output terminal of the second gate driver DR2 is connected to a gate G of the synchronous rectification transistor Q2. The drain D of the switching transistor Q1 is connected to a power terminal (high voltage potential terminal) Vin. The source S of the switching transistor Q1 is connected to a node N1. The drain D of the synchronous rectification transistor Q2 is connected to the node N1. The source S of the synchronous rectification transistor Q2 is connected to a ground terminal (low voltage potential terminal) GND. The inductor L is connected between the node N1 and a node N2. The capacitor C is connected between the node N2 and the ground terminal (low voltage potential terminal) GND. The smoothing circuit includes the inductor L and the capacitor C. The node N2 is connected to an output terminal OUT. A load RL is connected to the output terminal OUT. A CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a memory, or the like is connected as the load RL.
A source S of the third transistor Q3 is connected to the power terminal (high voltage potential terminal) Vin. A drain D of the third transistor Q3 is connected to a node N3. The node N3 is an output terminal of the series regulator SR. A gate G of the third transistor Q3 is connected to an output terminal of the error amplifier ERR. A non-inverting input terminal (+) of the error amplifier ERR is connected to the node N3. A reference voltage Vref is applied to an inverting input terminal (−) of the error amplifier ERR. An output voltage Vreg outputted to the node N3 as the output terminal of the series regulator SR is approximately equal to the reference voltage Vref. As such, the output voltage Vreg is set by the reference voltage Vref.
An anode of the diode Db is connected to the node N3. The capacitor Cb is connected between a cathode of the diode Db and the node N1. The bootstrap circuit BS includes the diode Db and the capacitor Cb.
The power terminal (high voltage potential terminal) of the first gate driver DR1 is connected to the cathode of the diode Db. A low voltage potential terminal of the first gate driver DR1 is connected to the node N1. The output voltage Vreg of the series regulator SR is applied to a power terminal (high voltage potential terminal) of the second gate driver DR2. A ground terminal (low voltage potential terminal) of the second gate driver DR2 is grounded.
Next, the signal flow and the circuit operation of the DC/DC converter including the bootstrap circuit of FIG. 7 are described below.
The control circuit DRV inputs a control signal to each of the first gate driver DR1 and the second gate driver DR2, for example, in response to a signal from a PWM comparator (not shown) or the like.
The first gate driver DR1 amplifies the control signal from the control circuit DRV and generates the drive signal S1. The switching transistor Q1 is driven by the drive signal S1. The second gate driver DR2 amplifies the control signal from the control circuit DRV and generates the drive signal S2. The synchronous rectification transistor Q2 is driven by the drive signal S2. Thus, the switching transistor Q1 and the synchronous rectification transistor Q2 are turned on or off in a complementary manner, and a current IL flows into the inductor L. The current IL is smoothed by the capacitor C and an output voltage Vout is generated on the output terminal OUT. When the load RL is connected to the output terminal OUT, an output current Tout is outputted.
The error amplifier ERR in the series regulator SR compares the reference voltage Vref and a supply voltage yin of the power terminal (high voltage potential terminal) Vin, and controls an on/off state of the third transistor Q3. As a result, the predetermined voltage Vreg is supplied to the bootstrap circuit BS.
Due to the output voltage Vreg of the series regulator SR, a charging current Ib0 flows into the diode Db of the bootstrap circuit BS and the capacitor Cb is charged. Thus, a sum of the supply voltage yin and a voltage Vreg−Vd (which is the voltage that is lowered from the output voltage Vreg of the series regulator SR by a forward voltage Vd of the diode Db), i.e., a voltage vin+Vreg−Vd, is applied to the power terminal (high voltage potential terminal) of the first gate driver DR1. This voltage higher than the supply voltage yin ensures that the switching transistor Q1 is turned on. As described above, the bootstrap circuit BS sets a high level H of the drive signal S1 to the sum of the supply voltage yin and the voltage Vreg−Vd (which is the voltage that is lowered from the output voltage Vreg of the series regulator SR by the forward voltage Vd of the diode Db), i.e., the voltage vin+Vreg−Vd. A low level L of the drive signal S1 is 0V. As such, the high level H of the drive signal S1 is set to a voltage higher, for example, by 3V to 5V than the supply voltage yin of the power terminal (high voltage potential terminal) Vin.
FIG. 8 is a timing chart for the operation of the DC/DC converter of FIG. 7. Hereinafter, the operation of the DC/DC converter is described below with reference to FIGS. 7 and 8.
In a time period from time t0 to time t1, since the level of the drive signal S1 is 0V, the switching transistor Q1 is in the off state. Since the level of the drive signal S2 is Vreg, the synchronous rectification transistor Q2 is in the on state. In addition, the level of the node N3 is Vreg and the level of the node N1 is 0V. Accordingly, the capacitor Cb is charged as the charging current Ib0 flows into the capacitor Cb. Prior to time t0, for example, the energy is stored in the inductor L and a voltage due to a counter-electromotive force is generated across the inductor L. Therefore, in the time period from time t0 to time t1, the current IL flows from the ground terminal (low voltage potential terminal) GND into the inductor L through the synchronous rectification transistor Q2.
In a time period T12 from time t1 to time t2, since the level of the drive signal S1 is 0V, the switching transistor Q1 is in the off state. Since the level of the drive signal S2 is changed from Vreg to 0V, the synchronous rectification transistor Q2 is switched from the on state to the off state. Here, the parasitic diode D2 exists in the synchronous rectification transistor Q2. In addition, the energy is stored in the inductor L and a voltage due to a counter-electromotive force is generated across the inductor L. Thus, the current IL flows from the ground terminal (low voltage potential terminal) GND into the inductor L through the parasitic diode D2. Therefore, a voltage drop corresponding to a forward voltage Vf of the parasitic diode D2 occurs on the node N1 and the level of the node N1 is changed from 0V to −Vf. In addition, the level of the node N3 remains at Vreg. Although the level of the node N3 remains constant, since the level of the node N1 is lowered from 0V to −Vf, the charging current Ib0 flowing into the capacitor Cb is increased.
In a time period from time t2 to time t3, since the level of the drive signal S1 is changed from 0V to vin+Vreg−Vd by the bootstrap circuit BS, the switching transistor Q1 is switched from the off state to the on state. On the other hand, since the level of the drive signal S2 remains at 0 v, the synchronous rectification transistor Q2 remains in the off state. In addition, the level of the node N3 remains at Vreg. The level of the node N1 is changed from −Vf to Vsw which is substantially equal to the supply voltage vin. Therefore, the charging current Ib0 does not flow into the capacitor Cb. In addition, since the current IL flows from the power terminal (high voltage potential terminal) Vin into the inductor L through the switching transistor Q1, the energy is stored in the inductor L.
In a time period from T34 time t3 to time t4, since the level of the drive signal S1 is changed from vin+Vreg−Vd to 0V, the switching transistor Q1 is switched from the on state to the off state. Since the level of the drive signal S2 is 0V, the synchronous rectification transistor Q2 remains in the off state. In this case, the energy is stored in the inductor L and a voltage due to a counter-electromotive force is generated across the inductor L. Thus, the current IL flows from the ground terminal (low voltage potential terminal) GND into the inductor L through the parasitic diode D2. Accordingly, a voltage drop corresponding to the forward voltage Vf of the parasitic diode D2 occurs on the node N1 and the level of the node N1 is changed from Vsw to −Vf. In addition, the level of the node N3 remains at Vreg. Although the level of the node N3 remains constant, since the level of the node N1 is lowered from Vsw to −Vf, the charging current Ib0 flows into the capacitor Cb in a larger amount than the case where the level of the node N1 is lowered from Vsw to 0V.
After time t4, the same operation as in the time period from time t0 to time t4 is repeated. Therefore, every time the switching transistor Q1 and the synchronous rectification transistor Q2 are turned off at the same time, the charging current Ib0 flows into the capacitor Cb. This results in an increased power consumption of the DC/DC converter.
As described above, in the synchronous rectification DC/DC converter, in order to prevent a through-current which occurs when the high side switching transistor Q1 and the low side synchronous rectification transistor Q2 are turned on at the same time, a dead time for which both of the switching transistor Q1 and the synchronous rectification transistor Q2 are turned off at the same time is provided. In the dead time, due to the parasitic diode D2 formed in the synchronous rectification transistor Q2, the voltage potential between the switching transistor Q1 and the synchronous rectification transistor Q2 is lower than the voltage potential at the source side of the synchronous rectification transistor Q2 by −Vf. Accordingly, in the time period T12 and the time period T34, every time both of the high side switching transistor Q1 and the low side synchronous rectification transistor Q2 are turned off, the wasteful charging current Ib0 flows into the internal capacitor Cb of the bootstrap circuit BS. This results in an increased power consumption of the DC/DC converter.
Various solutions have been taken to solve the above problem.
As a solution, there has been proposed a switching power supply circuit in which a charging current flowing into a capacitor of a bootstrap circuit is stopped when a high side transistor is turned on, which may result in a reduction in power consumption by the amount of the charging current.
As another solution, there has been proposed a semiconductor integrated circuit in which when a charge pump is in at a standby state of not performing a stepping-up operation, a high side transistor and a low side transistor are in an off state and a current does not flow into a resistance voltage dividing circuit to detect a step-up voltage only with a capacitance voltage dividing circuit. With the above configuration, the power consumption is reduced in the standby state.
In the above-proposed switching power supply circuits, when the high side transistor is turned on, the charging current flowing into the capacitor of the bootstrap circuit is stopped. However, this technique does not disclose how to prevent the charging current from flowing into the capacitor of the bootstrap circuit in a dead time.
The above-proposed semiconductor integrated circuits do not disclose how to prevent a charging current from flowing into a capacitor of a bootstrap circuit in a dead time.